The present inventive concept is generally related to data transfer circuits, integrated circuit devices incorporating data transfer circuits, and methods controlling the operation of a data transfer circuit that compensates for clock signal jitter arising as a function of power supply voltage variations.
As greater data bandwidth and enhanced functionality are increasingly demanded of integrated circuit devices, the transmission frequency for data received by and transmitted from such devices has increased. Increasing data input/output (I/O) frequencies causes many problems since conventional circuits are generally ill-adapted to function at such frequencies. For example, as data passes through certain data transfer circuits at higher and higher speeds, the tolerance of the data transfer circuit to variations in applied control signals and control voltages is diminished.
FIG. 1 is a block diagram of a generic data transfer circuit 100. The data transfer circuit 100 may take many different forms within a variety of integrated circuit devices, such as (e.g.) a data I/O interface for a semiconductor memory device. Within this exemplary context, as the operating frequency of a semiconductor memory device rises, the rate at which data passes through the I/O interface during read/write operations also increases.
As illustrated in FIG. 1, the data transfer circuit 100 essentially receives as inputs; a clock signal (CLK), a power supply voltage (Vp), and a data input signal (Din). In its operation, the data transfer circuit 100 provides output data (Dout) having the same information content as the input data (Din) synchronously with the clock signal (CLK). The information content of the output data (Dout) should be exactly the same as the input data (Din), albeit potentially retimed as an output from the data transfer circuit 100 so to be synchronously related to the clock signal (CLK).
Any particular design of the data transfer circuit 100 assumes a fixed value (i.e., a constant level) for the applied power supply voltage (Vp). Depending on the nature and application of the data transfer circuit 100, the power supply voltage (Vp) may take one of many different forms and be set at any reasonable level. For example, a voltage commonly generated within or applied to contemporary integrated circuit devices, such as VDD, VSS, VDDQ, VSSQ, VDDL, and VDDH, may be used as a power supply voltage (Vp) applied to the data transfer circuit 100.
However defined, the power supply voltage (Vp) is expected to power the internal circuits of the data transfer circuit 100 at a particular level. Thus, the components (e.g., transistors) and circuitry implementing the data transfer circuit 100 are designed under an assumption that a fixed value power supply voltage will be consistently applied. Of course, those skilled in the art understand that there are significant differences between ideal approaches to the generation and application of a power supply voltage and the real-life difficulties of providing a stable power supply voltage. It is understood, for example, that the level of a power supply voltage applied to a data transfer circuit will typically fluctuate up and down in response to transient noise, loading effects, etc. And such minor fluctuation in the level of a power supply voltage was historically well-tolerated, at least in relation to data transfer circuits. Unfortunately, the increasing rate at which data passes through certain data transfer circuits has greatly reduced the tolerance of such circuits to fluctuating power supply voltages.
Consider the example illustrated in FIG. 2, inclusive of FIGS. 2a, 2b, 2c and 2d. 
FIG. 2a comparatively illustrates the difference between an ideal power supply voltage stably set at a medium (or nominal) value VpM over a defined time period, and a noisy power supply voltage that varies from the nominal value VpM either upward to VpH or downward VpL as a function of noise at randomly occurring time periods within the defined time period.
FIG. 2b is a model circuit illustrating relationships between the clock signal (CLK), the applied power supply voltage (Vp), and a resulting jittered clock signal (Jittered CLK) that arise in conventional implementations of the data transfer circuit 100 previously described in relation to FIG. 1. FIGS. 2c and 2d are respective waveform timing diagrams further illustrating a case wherein the noisy power supply voltage of FIG. 2a is applied to the data transfer circuit 100 of FIG. 1. As may be understood from these related diagrams, a clock signal (CLK) is applied to the data transfer circuit 100 of FIG. 2a along with a data input signal (Din) and the power supply voltage (Vp). Ideally, the power supply voltage (Vp) would be fixed at the nominal level (i.e., would be unvaryingly stable at the level of VpM) over the multiple clock cycles shown in FIG. 2. Instead, the noisy power supply voltage (Vp) shown in FIG. 2a is a bad case scenario in which considerable fluctuation exists in the level of the power supply voltage (Vp) as it is applied to the data transfer circuit 100. In this regard, noise may be coupled onto the signal line(s) providing the power supply voltage (Vp) to the data transfer circuit 100. Under the influence of this “Vp noise”, the actual level of the power supply voltage (Vp) rises and falls (e.g.) between the VpM and VpL levels.
As conceptually illustrated in FIGS. 2b and 2c, a delayed but otherwise unaltered version of the clock signal (CLK) that should desirably operate within the data transfer circuit 100 to gate the input data (Din) through the data transfer circuit 100 as output data (Dout). However, certain components (e.g., transistors) within the circuitry implementing the data transfer circuit 100 respond to the noisy power supply voltage by running relatively faster during periods of elevated power supply voltage, and slower during periods of reduced power supply voltage. This relationship is illustrated in some additional detail in FIG. 2c. 
Referring to FIG. 2c, an ideal delayed clock signal is illustrated by the second timing signal waveform directly below the clock signal (CLK) waveform. This ideal delayed clock signal is characterized by a nominal delay period (TdM) that corresponds to the nominal level (VpM) of the ideal power supply voltage (Vp). Under ideal operating assumptions, each period of the delayed clock signal would have a uniform duration, but this is rarely, if ever, the case in real life. The third signal waveform shown in FIG. 2c illustrates a case wherein an elevated level (VpH) for the power supply voltage (Vp) results in a faster operation of constituent components within the data transfer circuit 100 and an accelerated transition (TdH verses TdM) in the delayed clock signal. Analogously, the fourth signal waveform shown in FIG. 2c illustrates a case wherein a reduced level (VpL) for the power supply voltage (Vp) results in a slower operation of constituent components within the data transfer circuit 100 and a further delayed transition (TdL verses TdM) in the delayed clock signal. The respective acceleration and further delay of the delayed clock signal transitions results in the development and effective application of a “jittered” clock signal within the data transfer circuit 100.
Referring now to FIG. 2d, when the level of the power supply voltage (Vp) is reduced during periods (3), (5), (8), and (10), and when the level of the power supply voltage (Vp) is elevated during (e.g.) periods (2), (4), (7), and (12), false clock edges (i.e., erroneous or transient clock signal transitions) are generated. The presence of these false clock edges (including e.g., the accelerated (+TdH) or further delayed (+tdL) clock signal transitions) caused by variations in the level of the applied power supply voltage (Vp) effectively yield the Jittered clock signal shown in FIG. 2d. 
The disastrous effect of the Jittered clock signal on the transfer of the input data (Din) through the data transfer circuit 100 is also illustrated in FIG. 2d. Ideally, the output data (Dout) would be a slightly and consistently delayed (+TdM) version of the “0”, “1”, “0”, “1” . . . bit sequence defined by the input data (Din). However, the false clock edges and uneven clock periods provided by the Jittered clock signal result in multiple erroneous input data (Din) gating operations and the provision of data content-erroneous output data (Dout).
FIG. 3 conceptually illustrates how the regularly applied input clock signal (CLK) in its operative application within the data transfer circuit 100 is converted into a “jittered” clock signal (Jittered CLK) by the presence of the Vp noise. And because the provision of the output data signal (Dout) from the data transfer circuit 100 is synchronous with the clock signal actually applied to the constituent circuits (i.e., the jittered clock signal), the output data (Dout) is altered in its information content relative to the input data signal (Din).
In final result, the timing windows during which each bit of input data (Din) must be coherently transferred from the data transfer 100 circuit as corresponding output data (Dout) shrink as the transfer rate for data passing through the data transfer circuit 100 rises. Such shrinking data transfer windows are less tolerant of the transient or false edges in a clock signal controlling the synchronous output of data from a data transfer circuit. Accordingly, data transfer circuits finding application in high speed integrated circuits are unacceptably susceptible to output data errors caused by noisy or variable power supply voltage(s). And as contemporary integrated circuits are increasingly dense in their integration, the risk of power supply voltage noise (e.g., package inductance noise, printed circuit board noise source coupling, on-chip IR drop, signal line-to-power line cross coupling, etc.) increases.
The difference in information content between the output data (Dout) and input data (Din) of FIG. 2 is exemplary of a worst case scenario in which power supply voltage noise causes significant loss in data coherency.